1. Field of the Invention
The present invention relates to a method for manufacturing a silicon wafer obtained by slicing a silicon single-crystal ingot produced by the Czochralski method, and to a technology appropriate for suppressing slip dislocations to improve wafer mechanical strength.
The present invention contains subject matter related to Japanese Patent Application No. 2004-214983, filed on Jul. 22, 2004, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Single-crystal silicon wafers used as substrates for semiconductor devices and the like are manufactured by slicing a silicon single-crystal ingot and performing heat treatment, mirror polishing, and other processing. Methods for manufacturing such silicon single-crystal ingots include for example the Czochralski method (CZ method). Because the CZ method can be used to manufacture single-crystal ingots having large diameters and because defect control is comparatively easy, this method is the main method employed in the method for manufacturing the silicon single-crystal ingots.
In order to form semiconductor devices on single-crystal silicon wafers, it is required that there is no crystal defects in a device formation area. In the case in which the crystal defects exist in the surface in which circuitry is formed, the defect portion may be the cause of circuit breakdown or other problems. A silicon single crystal pulled using the CZ method includes a supersaturated concentration of oxygen atoms at interstitial lattice sites. This supersaturated oxygen causes an occurrence of micro defects which are called BMDs (bulk micro defects) during annealing treatment in subsequent bulk processes.
On the other hand, because such BMDs act as getters for metal impurities and other causes of crystal defects, a DZ-IG method is known in which an IG (intrinsic gettering) layer acting as an impurity getter is formed by annealing a silicon wafer to cause BMDs within the wafer, and a DZ (denuded zone) layer with no lower limit to the crystal defect is formed at the silicon wafer surface.
However, in subsequent manufacturing or device fabrication entailing processes, there is a problem that when annealing a silicon wafer in which such a DZ (denuded zone) layer is formed, dislocation defects (slip) tend to occur within the wafer. Particularly when annealing is performed in a state in which the wafer is supported by a heat treatment boat or similar, slip dislocations tend to propagate from the portions being supported on the rear surface of the wafer, resulting in a damage to the wafer during manufacturing processes, and possibly culminating in a destruction of the wafer. Consequently, as disclosed in Patent Reference 1, a method is proposed in which damage (contact damage) to the rear surface of the wafer arising from contact of the silicon wafer with the heat treatment boat during a heat treatment to form a DZ layer is removed by etching or by mechanical polishing, to suppress the occurrence of dislocation defects (slip).
However, because the silicon wafer in which the DZ layer is formed is in a state in which a oxygen concentration in the DZ zone is extremely low due to outward diffusion of oxygen, the wafer strength is inherently low, and in the case in which minute abrasions, dislocations, or the like occur during annealing processes in the course of device fabrication or the like, slip dislocations easily propagate. Therefore, there is a problem that the occurrence of dislocation defects (slip) cannot be adequately suppressed merely by removal of the damage layer on the rear surface of the wafer.    Patent Reference 1: Japanese published unexamined patent application No. 2002-134521